Neutron uses a fixed physical address layout defined for the BCM2837/BCM2710 SoC. All addresses in this page are physical; the bootloader and kernel run with the MMU disabled.
RAM Layout
| Address | Size | Purpose |
|---|---|---|
| 0x80000 | varies | Bootloader (kernel8.img). Loaded here by the GPU or QEMU. Stack grows downward from this address. |
| 0x100000 | 4 MiB | Kernel staging (SD path). The packed kernel file (name from kernel_filename) is read from the SD card into this region. The bootloader parses the NKRN header here and copies the payload to the load address. |
| 0x200000 | varies | Kernel load and entry. The payload of the packed kernel is copied here. The bootloader jumps to this address with x0 set to the boot info pointer. |
| 0x1000 | 64 B | boot_info_t. Written by the bootloader before the jump. Contains magic, board revision, ARM memory size, kernel load/entry/size, and bootloader version string. |
Constants are defined in internal/platform.h and build.cfg/internal/config.h (for staging/load addresses). The bootloader linker script linker/bootloader.ld sets the load address to 0x80000; the test kernel linker script test_kernel/linker/kernel.ld uses 0x200000.
The staging area at 0x100000 is overwritten when the bootloader reads the packed kernel from SD (SD path). The payload is copied to 0x200000 so the kernel runs from a clean region. Do not assume any content at 0x100000 after the copy.
Peripheral Base (MMIO)
Peripherals are memory-mapped with base address 0x3F000000 (BCM2837). Key registers:
| Address | Peripheral |
|---|---|
| 0x3F000000 | MMIO base (platform constant MMIO_BASE) |
| 0x3F200000 | GPIO (GPIO_BASE) |
| 0x3F201000 | PL011 UART0 (UART0_BASE). Used for serial console. |
| 0x3F202000 | SDHOST. SD card controller used by QEMU raspi3b. |
| 0x3F00B880 | Mailbox (MBOX_BASE). VideoCore property channel. |
All accesses are 32-bit. The UART is configured for 115200 baud with a 48 MHz reference clock (divisors IBRD=26, FBRD=3). GPIO pins 14 and 15 are set to alternate function 0 (TXD0, RXD0) for UART0.
Bootloader Image Layout
The bootloader binary is linked so that the first instruction (_start) is at offset 0. Sections appear in this order:
.text.boot: Entry and early assembly (park cores, EL2 to EL1)..vectors: Exception vector table, 0x800-byte aligned..text,.rodata,.data: Code and data..bss: Zero-initialised data (cleared bystart.S).
The symbol _stack_top is set to 0x80000; the stack pointer is initialised to this value so the stack grows downward and does not overlap the bootloader image.
References
include/neutron.h: Shared MMIO defs andboot_info_tABI.internal/platform.h: Bootloader-specific platform constants and mailbox tags.linker/bootloader.ld: Bootloader section layout and load address.- Boot Flow: How these regions are used during boot.